Q) What is CPU memory access granularity?
Q) What is the principle of CPU memory access alignment?
Q) What happen when CPU try to access an non align memory address, How it handles the un align address access?
Q+Expain) When a pointer variable is pointing to NULL and then you access that pointer variable, What exactly happen that the program terminates.? Explain the answer in Hardware software interaction point of view.
Q) How memory barrier and cache coherency relate to each other, Explain using simple abstract CPU messaging interactions.?
Q) How X 86 “lfence”, “sfence”, “mfence”, “lock” works and when should they be used in program. What are the guarantee they offer and what are the things which should not be assumed about these instructions?
Q) Assume that there are multiple CPU core modern ( like X86 ) are available in a machine, You have to pull the latest data [ memory region ] from all other cores in to core 1 how will you do this in program?
Q) What is the difference between registers, store buffer, load buffer, invalidate buffer and write combine buffer?
Q) What exactly a cache line is and what are the things stored in a cache line and what is cache line size, Is this related to cache size? and How many cache lines can be there in a CPU architectures?
Explain) Explain the below statements about “false sharing” in details “since caches operate on the granularity of cache lines and not individual bytes, the entire cache line will be invalidated in all caches”.
Q) How will you separate the cache line to be used by two different threads in two different cores and Hence avoid the core dance for the same cache line. [ Cover the case of SPSC on an array based queue]